FIG. 65 is an explanatory view of a conventional thin film transistor 900.
As shown in FIG. 65, the conventional thin film transistor 900 includes a source electrode 950, a drain electrode 960, a channel layer 940 located between the source electrode 950 and the drain electrode 960, a gate electrode 920 for controlling a conductive state of the channel layer 940, and a gate insulating layer 930 provided between the gate electrode 920 and the channel layer 940 and made of a ferroelectric material. In FIG. 65, reference sign 910 denotes an insulating substrate.
In the conventional thin film transistor 900, used as a material for the gate insulating layer 930 is a ferroelectric material (such as BLT (Bi4-xLaxTi3O12) or PZT (Pb(ZrxTi1-x)O3)). Furthermore, an oxide conductive material (such as indium tin oxide (ITO)) is used as a material for the channel layer 940.
In the conventional thin film transistor 900, such an oxide conductive material is used as a material for the channel layer, thereby increasing carrier density. Furthermore, the ferroelectric material is used as a material for the gate insulating layer, thereby realizing quick switching at a low drive voltage. Achieved as a result is quick control on a large current at a low drive voltage.
The conventional thin film transistor can be produced in accordance with a method of producing a conventional thin film transistor, as shown in FIGS. 66(a) to 66(f). FIGS. 66(a) to 66(f) are explanatory views of the method of producing a conventional thin film transistor. FIGS. 66(a) to 66(e) show the respective processes. FIG. 66(f) is a plan view of the thin film transistor 900.
Initially, as shown in FIG. 66(a), there is formed, on an insulating substrate 910 that is made of an Si substrate provided on a surface thereof with an SiO2 layer, the gate electrode 920 as a laminated film made of Ti (10 nm) and Pt (40 nm), in accordance with the electron-beam evaporation technique.
Then, as shown in FIG. 66(b), formed from above the gate electrode 920 in accordance with the sol-gel method is the gate insulating layer 930 (200 nm) which is made of BLT (Bi3.25La0.75Ti3O12) or PZT (Pb(Zr0.4Ti0.6)O3).
Subsequently, as shown in FIG. 66(c), the channel layer 940 (5 nm to 15 nm) made of ITO is formed on the gate insulating layer 930 in accordance with the RF-sputtering technique.
Thereafter, as shown in FIG. 66(d), Ti (30 nm) and Pt (30 nm) are deposited on the channel layer 940 in accordance with the electron-beam evaporation technique, so that there are formed the source electrode 950 and the drain electrode 960.
Then, the element region is isolated from a different element region in accordance with the RIE method and the wet etching method (HF:HCI liquid mixture).
Produced as a result is the thin film transistor 900 illustrated in FIGS. 66(e) and 66(f).
FIG. 67 is an explanatory view of electrical properties of the conventional thin film transistor 900. In FIG. 67, reference sign 940a denotes a channel, and reference sign 940b denotes a depletion layer.
As shown in FIG. 67, the conventional thin film transistor 900 obtains approximately 10−4 A as an ON-state current at a gate voltage of 3 V (VG=3 V), 1×104 as an ON/OFF ratio, 10 cm2/Vs as an electron field-effect mobility μFE, and approximately 2 V as a memory window property.